Loop Rerolling for Hardware Decompilation

We introduce the new problem of hardware decompilation . Analogous to software decompilation, is about analyzing a low-level artifact—in this case netlist , i.e., graph wires and logical gates representing digital circuit—in order recover higher-level programming abstractions, using those abstractions generate code written in description language (HDL). The overall requires number pieces. In paper we focus on one specific piece puzzle: technique call loop rerolling Hardware leverages clone detection program synthesis techniques identify repeated logic netlists (such as would be synthesized from loops original HDL code) reroll them into syntactic recovered code. evaluate for over set design benchmarks PyRTL industry standard SystemVerilog. Our implementation identifies rerolls 52 out 53 our benchmark suite, show three examples how can provide concrete benefits: transpilation between HDLs, faster simulation times (with mean speedup 6x), artifact compaction (39% smaller average).